The present invention relates to a method for producing, in the manufacturing of an integrated circuit in a bipolar process, a collector pin and a trench for isolating the semiconductor components comprised in the integrated circuit, and to the collector pin, the trench and the integrated circuit. The collector pin, the trench and the integrated circuit are primarily intended for radio applications or other high-speed communication where components with good performance characteristics are required.
Traditionally, when manufacturing integrated circuits, so called LOCOS (Local Oxidation of Silicon) isolation is used in combination with junction isolation, to isolate the components of the integrated circuit; see, for example, J.A. Appels et al, xe2x80x9cLocal Oxidation of Silicon and its application in Semiconductor Technology,xe2x80x9d, Philips Res. Rep. vol. 25, 1970, pp. 118-132.
In the manufacturing of bipolar components for RF-IC (Radio Frequency-Integrated Circuits) applications, it is common to isolate the individual components in the silicon substrate from each other with etched trenches instead; see, for example, U.S. Pat. Nos. 4,139,442, 4,789,885, P. C. Hunt et al., xe2x80x9cProcess HE: A Highly Advanced Trench Isolated Bipolar Technology for Analogue and Digital Applicationsxe2x80x9d, Proc. IEEE 1988 Custom and Integr. Circuits Conf. Rochester N.Y. May 16-19 1988, and A. Hayasaka et al., xe2x80x9cU-Groove Isolation Technique for High Speed Bipolar VLSI""sxe2x80x9d, Proc. IEDM 1982 p. 62.
The technique of trench isolation has also been used for isolating CMOS components, although to a considerably smaller extent, see for example R. D. Rung et. al, xe2x80x9cDeep trench isolated CMOS Devicesxe2x80x9d, IEDM, Techn. Dig. Paper 9.6, 1982.
By means of a trench, etched deeply into the silicon, and surrounding a semiconductor component, such as, for example, a bipolar transistor, the capacitance between the bottom diffusion layer and the substrate can be reduced substantially. At the same time better isolation between adjacent components is achieved, that is, an increased immunity against cross talk, while the dimensions of the transistor cell may be reduced at the same time.
Another advantage of trench isolation is that the trenches may be made so deep, approx. 5-10 xcexcm, that they extend through the entire epi-layer of the plate, that is, the active surface layer, all the way down to a heavily doped silicon substrate of low resistance. Thus, the isolating properties and the risk for latch-up are reduced, see for example V. dela Torre et al., xe2x80x9cMOSAIC V-A Very High Performance Bipolar Technologyxe2x80x9d, Proc. BCTM 1991, p. 21.
Below, and in connection with the FIGS. 1-3, a commonly used method for making a trench when manufacturing a bipolar transistor of npn type is described.
As starting material a low doped p type monocrystalline silicone substrate 1 of(100) orientation, shown in FIG. 1, is used. A heavily doped bottom diffusion layer of n type, or a buried collector layer 2, which may be made of, for example, an ion implanted layer of arsenic or antimony, is created, whereafter an epitaxic silicon layer 3 of n type is applied with a thickness of approximately 1-2 xcexcm.
At least two variations as to where the so called trench module may be integrated in the process flow are known from the literature. According to a first variation, described by, for example the mentioned P. C. Hunt et al. and U.S. Pat. No. 4,983,226, the trench processing is performed before the definition (with LOCOS technique) of the field areas. According to the second variation, disclosed in, among other documents, EP 0, 724, 291 A2, the trench is created after the definition of the field areas. Both variations aim at the same final result, and in the following, only the first variation will be described.
A layer 4, approximately 1 xcexcm thick, of LPCVD (Low Pressure Chemical Vapor Deposition) oxide, which will function as a hard mask, is then deposited over the plate. Trench openings 5a are then defined in a lithographic way, whereafter the oxide layer 4 is etched back to reveal the underlying silicon surface. Then all photo resist is removed from the structure, whereafter the epitaxial layer 3, the bottom diffusion layer 2 and the silicon substrate 1 are etched back using an anisotropic dry etching until a trench 5 of a predetermined depth, approximately 5-10 xcexcm has been created (see FIG. 1).
As the substrate is made up of lightly doped p type material, usually a small dose of low energy boron is implanted in the bottom of the trench 5 to achieve a channel stop 6, see FIG. 2. The channel stop 6 reduces the current amplification of the parasite transistor (n+bottom diffusion layer/pxe2x88x92substrate/n+bottom diffusion layer) which is created and which increases the threshold voltage for the corresponding parasite MOS transistor. If, on the other hand, an epi-material of pxe2x88x92/p+ type is used as a starting material, no such implant is needed.
After the etching of the trench and the implantation of ions the hard mask 4 is removed, whereafter the semiconductor structure is oxidised thermally until a silicon oxide 7 approximately 100 nm is obtained. Then a thin silicon nitride layer 8 is deposited over the semiconductor structure, especially in the trench 5, whereafter the trench is filled with polysilicon 9. Alternatively an insulating or semi-insulating substance, for example silicon oxide may be used, as described in U.S. Pat. No. 4,139,442 or the above mentioned R. D. Rung et al. The filling material, which in Hunt""s article is made up of polysilicon, is etched back with dry etching until the silicon nitride layer 8 is uncovered outside the trench opening 5a. 
After the filling substance 9 has been etched back, the silicon nitride layer 8 is masked and etched, whereafter silicon is oxidized by means of conventional LOCOS technique for creating both thick field oxide areas 10 and a cap oxide 11 over the trench opening, see FIG. 3. If the trench 5 is already filled with oxide from the beginning, of course no additional cap oxidation is needed.
A collector pin 12, connecting the bottom diffusion layer 2 to the silicon surface, is obtained, whereafter remaining areas of the silicon nitride layer 8 and the silicon oxide layer 7 are removed. FIG. 3 shows the structure resulting from this. As an alternative, the collector pin 12 can be implanted before the trench processing, as described in U.S. Pat. No. 4,958,213.
The above described techniques have a number of drawbacks, which have led to a low yield being noticed when using trench isolation, see for example F. Yang et al. xe2x80x9cCharacterization of collector-emitter leakage in self-aligned double-poly bipolar junction transistorsxe2x80x9d, J. Electrochem. Soc., vol. 140, no. 10, 1993, p. 3033.
The commonly accepted explanation of the low yield when trench isolation is used is that the trench process (trench etching, sidewall oxidation, filling, re-etching and cap oxidation) introduces defects in the silicon substrate. A relatively detailed description of the problems of trench isolation and suggestions on how to avoid them have been the subject of a number of patents, see for example U.S. Pat. No. 4,983,226, EP 0, 278, 159 A2 and the above mentioned U.S. Pat. No. 4,958,213.
Also, the descriptions are not consistent, in the sense that in U.S. Pat. No. 4,958, 213 expresses the opinion that a thickness of the sidewall oxide in the trench of approximately 100 nm functions satisfactorily, whereas in U.S. Pat. No. 4,983,226 an upper limit of 45 nm is recommended for the thickness of the oxide layer. Otherwise, according to U.S. Pat. No. 4,983,226, unnecessary mechanical stress, and thereby dislocations, will be created.
In EP 0, 278 159 A2 it is described how a thin layer of polysilicon is deposited on the inside of the trench, which is later converted, in thermal oxidation, to oxide on the inside of the trench. In this way, unnecessarily heavy oxidation is avoided, and the mechanical tension or stress is reduced.
U.S. Pat. No. 4,958,213 expresses the opinion that the cap oxidation step creates problems. Therefore it is suggested in a final step to refill the upper part of the trench opening with a deposited oxide to reduce the mechanical tension caused by the creation of so-called bird""s beaks at cap oxidation. The suggestion both involves complicated process techniques and high manufacturing costs, since it requires two filling steps, which are independent, and following planarization.
In, for example, U.S. Pat. No. 4,983,226, the use of cap oxide, which is simpler, is described. To eliminate the presence of vertical bird""s beaks, it is suggested to use a thin layer of silicon nitride on top of the sidewall oxide in the trench and thereby minimize the mechanical stress. A similar method is described in the above mentioned P. C. Hunt et al.
In all the cases described above polysilicon or silicon oxide has been suggested as a filling material in the trenches. This may lead to the presence of voids in the filling, see for example FIG. 7, page 577 in R. D. Rung""s article.
An object of the present invention is to provide an integrated circuit having at least one isolating trench, especially an integrated circuit intended for radio applications or other high speed communication, which is reliable and has good performance characteristics.
Another object of the invention is to provide a trench isolated integrated circuit avoiding one or more of the problems that can arise with prior art.
Yet another object of the invention is to provide an integrated circuit with trenches having no dislocations.
A further object of the invention is to provide a reliable and uncomplicated manufacturing method for an integrated circuit having the above-mentioned properties. In particular, a manufacturing method giving a high yield is strived for.
Other objects of the present invention will become apparent from the description below.
A problem which has not yet been given attention, is that even an integrated circuit with a trench completely without dislocations may be unreliable, unless a collector pin comprised in the integrated circuit can be made without dislocations. At ion implantation of the collector pin according to prior art, defects or dislocations are introduced, especially screw dislocations, which may be confined to the area enclosed by the trench. These defects can then penetrate active p-n junctions, whereby an increased leakage current arises. In the worst case, such an integrated circuit becomes useless.
By recognizing this problem, a reliable integrated circuit without dislocations may be manufactured by combining a trench without dislocations, according to prior art, with a manufacturing method for a collector pin without dislocations.
According to the invention, this method involves providing a collector opening by revealing a predetermined area surrounded by field oxide on an upper surface of silicon in a semiconductor structure by means of etching, providing an area that has been implantation damaged, or made amorphous, and at least partially doped extending from the upper silicon surface down to a depth lower than the depth of the field oxide, implanting ions of a predetermined dose and energy through the upper silicon surface and by subsequently heat treating the semiconductor structure.
Preferably the area is achieved in two steps, the first of which comprises making the surface region of the area amorphous, especially by implanting heavy ions, such as for example arsenic or antimony ions. The second step involves doping the area from its surface region down, especially by letting light ions, such as phosphorus ions be implanted.
The heat treatment is also preferably performed in two steps. First the area is recrystallized from the bottom up by heat treatment, preferably at approximately 550-600xc2x0 C. for approximately xc2xd-1 hour. Then the doped ions, especially the phosphorus ions are caused to diffuse down towards a doped bottom diffusion layer comprised in the semiconductor structure by means of annealing, preferably at approximately 950xc2x0 C. for approximately 1 hour.
The invention also comprises an improved manufacturing method for the trench. An oxide layer, preferably of the kind PECVD (Plasma Enhanced Chemical Vapor Deposition) TEOS, is uniformly deposited over the semiconductor structure, especially in the trench. Before the filling of the trench a barrier layer of silicon nitride is deposited as well.
In more detail, the method according to the invention involves the deposition of a hard mask, especially an oxide layer of the kind PECVD (Plasma Enhanced Chemical Vapor Deposition) the deposition of TEOS over a semiconductor structure comprising an upper silicon surface, the creation of a trench opening by, through etching, uncovering of a predetermined area of the upper silicon surface, the creation of a trench by etching of the semiconductor structure within the predetermined area to a predetermined depth, the removal of the hard mask and the first silicon layer by means of etching, the uniform deposition of a first oxide layer, preferably of the kind LPCDV-TEOS, over the semiconductor structure, especially in the trench, the deposition of a barrier layer, preferably of silicon nitride uniformly over the first oxide layer, the depositing of a silicon layer over the silicon nitride layer, especially in the trench, to fill the trench, and the etching of the silicon layer until the underlying nitride layer is uncovered outside of the trench opening, and the thermal growing of a cap oxide over the trench opening.
Preferably the upper silicon surface is covered by an oxide before a first silicon layer, preferably of polysilicon, is deposited over the oxide before the hard mask is deposited.
The method according the invention may also comprise the creation of a tapered trench with a rounded bottom, wet etching and growing a thin thermal oxide before the first oxide layer is deposited, densifying the first oxide layer, depositing a second oxide layer on the nitride layer and filling the trench with microcrystalline silicon. Further improvement of the details will become apparent from the description below.
By means of the present invention, a reliable integrated circuit, with a trench that meets the requirements well, is obtained.
An advantage of the invention is that a relatively simple trench, substantially dislocation-free, may be used in combination with the collector pin according to the invention.
Another advantage is that when an oxide is deposited in the trench less tension is caused than if the oxide is grown thermally. Thus, the oxide may be deposited as a thicker layer, for example approximately 100-200 nm thick, which gives better isolation. If the oxide is densified, the isolating properties will be further improved.
Yet another advantage of the invention is that if the trench is given a tapered shape with a rounded bottom, the risk of mechanical tension and the creation of voids at the filling is reduced. This risk is further reduced if microcrystalline silicon is used for the filling.